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| CY2SSTU32866 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register with Parity Features * Operating frequency: DC to 500 MHz * Supports DDRII SDRAM * Two operations modes: 25 bit (1:1) and 14 bit (1:2) * 1.8V operation * Fully JEDEC-compliant (JESD 82-10) * 96-ball FBGA CSR# inputs are HIGH. If either DCS# or CSR# input is LOW, the Qn outputs will function normally. The RESET# input has priority over the DCS# and CSR# control and will force the outputs LOW. If the DCS#-control functionality is not desired, the CSR# input can be hardwired to ground, in which case the set-up time requirement for DCS# would be the same as for the other D data inputs. The device supports low-power standby operation. When the reset input (RESET#) is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET# is LOW, all registers are reset and all outputs are forced LOW. The LVCMOS RESET# and Cn inputs must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the LOW state during power-up. In the DDR-II RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. Functional Description All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. The CY2SSTU32866 operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going LOW. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH). The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and Pin Configuration A B C D E F G H J K L M N P R T 1 DCKE D2 D3 DODT D5 D6 PAR_IN CK CK# D8 D9 D10 D11 D12 D13 D14 1 2 PPO D15 D16 QERR# D17 D18 RST# DCS# CSR# D19 D20 D21 D22 D23 D24 D25 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS# ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 5 6 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 6 A B C D E F G H J K L M N P R T 1 DCKE D2 D3 DODT D5 D6 PAR_IN CK CK# D8 D9 D10 D11 D12 D13 D14 1 2 PPO NC NC QERR# NC NC RST# DCS# CSR# NC NC NC NC NC NC NC 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 5 6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B 6 A B C D E F G H J K L M N P R T 1 D1 D2 D3 D4 D5 D6 PAR_IN CK CK# D8 D9 D10 DODT D12 D13 DCKE 1 2 PPO NC NC QERR# NC NC RST# DCS# CSR# NC NC NC NC NC NC NC 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A QODTA Q12A Q13A QCKEA 5 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B QODTB Q12B Q13B QCKEB 6 1:1 Register C0 = 0, C1=0 1:2 Register A C0 = 0, C1=1 1:2 Register B C0 = 1, C1=1 Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 24 www.SpectraLinear.com CY2SSTU32866 The CY2SSTV32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR# pin (active LOW). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. The partial-parity-out (PPO) and QERR# signals are produced three cycles after the corresponding data inputs. When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the second register is tied HIGH. The Table 1. Parity Function Table Inputs RESET# H H H H H H H H H H L DCS# L L L L H H H H H X X or Floating CSR# X X X X L L L L H X X or Floating L or H X or Floating L or H X or Floating CK CK# Sum of inputs = H (D1-25) Even Odd Even Odd Even Odd Even Odd X X X or Floating PAR_IN L L H H L L H H X X X or Floating PPO L H H L L H H L PPO0 PPO0 L Outputs QERR# H L L H H L L H QERR#0 QERR#0 H C1 input of both registers are tied HIGH. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the first device. The PPO and QERR# signals are produced on the second device three clock cycles after the corresponding data inputs. The PPO output of the first register is cascaded to the PAR_IN of the second register. The QERR# output of the first register is left floating and the valid error information is latched on the QERR# output of the second register. If an error occurs and the QERR# output is driven LOW, it stays latched LOW for two clock cycles or until RESET# is driven LOW. The DIMM-dependent signals (DCKE, DCS#, DODT, and CSR#) are not included in the parity check computation. Parity is calculated using Table 1. Pin Definition Pin Name GND Pin Number (C0 = 0, C1 = 0) Pin Number (C0 = 0, C1 = 1) Pin Number (C0 = 1, C1 = 1) Description B3, B4, D3, D4, F3, F4, B3, B4, D3, D4, F3, B3, B4, D3, D4, F3, Ground H3, H4, K3, K4, M3, M4, F4, H3, H4, K3, K4, F4, H3, H4, K3, K4, P3, P4 M3, M4, P3, P4 M3, M4, P3, P4 A4, C3, C4, E3, E4, G3, A4, C3, C4, E3, G4, J3, J4, L3, L4, N3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, N4, R3, R4, T4 R4, T4 A3, T3 J5 J6 H1 J1 G6 G5 A3, T3 J5 J6 H1 J1 G6 G5 A4, C3, C4, E3, Power Supply Voltage E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 A3, T3 J5 J6 H1 J1 G6 G5 Input Reference Voltage Reserved Reserved Positive Master Clock Negative Master Clock Configuration control input Configuration control input VDD VREF ZOH ZOL CK CK# C0 C1 Rev 1.0, November 25, 2006 Page 2 of 24 CY2SSTU32866 Pin Definition (continued) Pin Name RESET# G2 Pin Number (C0 = 0, C1 = 0) Pin Number (C0 = 0, C1 = 1) G2 Pin Number (C0 = 1, C1 = 1) G2 Description Asynchronous reset - resets registers and disables Vref data and clock differential input receivers Chip Select - Disables D1-D24 when both CSR# and DCS# are HIGH (VDD) Chip Select - Disables D1-D24 when both CSR# and DCS# are HIGH (VDD) Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# CSR# DCS# D1 D2-3 D4 D5, 6, 8, 9, 10 D11 D12, 13 D14 D15-25 DODT DCKE Q1A Q2A-3A Q4A J2 H2 J2 H2 J2 H2 A1 B1, C1 B1, C1 B1, C1 D1 E1, F1, K1, L1, M1 N1 P1, R1 T1 B2, C2, E2, F2, K2, L2, M2, N2, P2, R2, T2 D1 A1 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input - clocked in on the crossing points of CK and CK# N1 P1, R1 T1 P1, R1 Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# D1 A1 N1 T1 A5 The outputs of this register bit will not be suspended by the DCS# and CSR# Control The outputs of this register bit will not be suspended by the DCS# and CSR# Control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control B5, C5 B5, C5 B5, C5 D5 Q5A, 6A, 8A, E5, F5, K5, L5, M5 9A, 10A Q11A Q14A Q1B Q2B-3B Q4B Q5B, 6B, 8B, 9B, 10B, Q11B N5 T5 Q12A, Q13A P5, R5 E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS# and CSR# control N5 P5, R5 T5 A6 B6, C6 B6, C6 D6 P5, R5 Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS# and CSR# control N6 Data Outputs that are suspended by the DCS# and CSR# control Rev 1.0, November 25, 2006 Page 3 of 24 CY2SSTU32866 Pin Definition (continued) Pin Name Q12B, 13B Q14B Q15-25 QCSA# QCSB# QODTA QODTB QCKEA QCKEB PPO QERR# PAR_IN NC A2 D2 G1 A6, D6, H6 A5 D5 B6, C6, E6, F6, K6, L6, M6, N6, P6, R6, T6 H5 H5 H6 D5 D6 A5 A6 A2 D2 G1 H5 H6 N5 N6 T5 T6 A2 D2 G1 Pin Number (C0 = 0, C1 = 0) Pin Number (C0 = 0, C1 = 1) P6, R6 T6 Pin Number (C0 = 1, C1 = 1) P6, R6 Description Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Partial parity out - indicates odd parity of inputs D1-D25 Output error bit - generated one clock cycle after the corresponding data output Parity input - arrives one clock cycle after the corresponding data input B2, C2, E2, F2, K2, B2, C2, E2, F2, K2, No Connect Pins L2, M2, N2, P2, L2, M2, N2, P2, R2, T2 R2, T2 Table 2. Flip Flop Function Table RESET# H H H H H H H H H H H H L Inputs DCS# CSR# CK L L L L L L L or H L H L H L H L or H H L H L H L L or H H H H H H H L or H X or Floating X or Floating X or Floating CK# Dn, DODT, DCKE L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# QODT, QCKE L L L H Q0 Q0 L L L H Q0 Q0 H L H H Q0 Q0 H L H H Q0 Q0 L L L or H L or H L or H L or H X or Floating Rev 1.0, November 25, 2006 Page 4 of 24 CY2SSTU32866 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D2-D3, 22 D5-D6, D8-D25 A3, T3 VREF D R CE CLK Q D2-D3, D5-D6, D8-D25 D2-D3, D5-D6, D8-D25 22 22 22 Q2-Q3, Q5-Q6, Q8-Q25 Parity Generator C1 G5 0 D R PAR_IN G1 Q CLK R 1 D Q CLK CE R D Q CLK 1 0 A2 PPO D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R Figure 1. Parity logic Diagram for 1:1 register configuration (positive logic) C0=0, C1=0 Rev 1.0, November 25, 2006 Page 5 of 24 CY2SSTU32866 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D2-D3, 11 D5-D6, D8-D14 A3, T3 VREF D R CE CLK Q D2-D3, D5-D6, D8-D14 D2-D3, D5-D6, D8-D14 11 11 11 Q2A-Q3A, Q5A-Q6A, Q8A-Q14A Q2B-Q3B, Q5B-Q6B, Q8B-Q14B 11 Parity Generator C1 G5 0 D R PAR_IN G1 Q CLK R 1 D Q CLK CE R D Q CLK 1 0 A2 PPO D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R Figure 2. Parity logic Diagram for 1:2 register-A configuration (positive logic) C0=0, C1=1 Rev 1.0, November 25, 2006 Page 6 of 24 CY2SSTU32866 RESET CLK CLK G2 H1 J1 LPS0 (internal node) D1-D6, D8-D13 VREF 11 A3, T3 D R 11 D1-D6, D8-D13 CE CLK Q 11 D1-D6, D8-D13 11 Q1A-Q6A, Q8A-Q13A Q1B-Q6B, Q8B-Q13B 11 Parity Generator C1 G5 0 D R PAR_IN G1 Q CLK R 1 D Q CLK CE R D Q CLK 1 0 A2 PPO D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (internal node) 0 D Q CLK 1 R Figure 3. Parity logic Diagram for 1:2 register-B configuration (positive logic) C0=1, C1=1 Rev 1.0, November 25, 2006 Page 7 of 24 CY2SSTU32866 (RESET switches from L to H) RESET DCS CSR CLK CLK D1-D25 Q1-Q25 tsu PAR_IN th PPO tPHL CLK to QERR tPHL, tPLH CLK to QERR QERR Figure 4. CY2SSTU32866 used as single device C0=0, C1=0, RST# Switchs L to H Rev 1.0, November 25, 2006 IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII tact IIIIII IIIIII IIII IIII IIII IIIII IIIII IIIII n n+1 n+2 n+3 n+4 tsu th tpdm, tpdmss CLK to Q tpd CLK to PPO Data to QERR Latency H, L, or X H or L Page 8 of 24 CY2SSTU32866 RESET DCS CSR CLK CLK D1-D25 Q1-Q25 PAR_IN PPO QERR Unknown input event Rev 1.0, November 25, 2006 C CCCCCCCCCCCCCC CCCCCCCCCCCC C CCCCCCCCCCCCCC CCCCCCCCCCCCCC C CCCCCCCCCCCC C CCCCCCCCCCCCCC Figure 5. CY2SSTU32866 used as single device, C0=0, C1=0, RST# being held high CCCC CCCC CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC I IIIII III I IIIII IIII IIII IIII I IIII III IIII III III III III III III tsu n n+1 n+2 n+3 n+4 th tpdm, tpdmss CLK to Q tsu th tpd CLK to PPO Data to PPO Latency tPHL or tPLH CLK to QERR Data to QERR Latency EEEE EEEE Output signal is dependent on the prior unknown input event H or L Page 9 of 24 CY2SSTU32866 RESET tinact DCS CSR CLK CLK D1-D25 tRPHL RESET to Q Q1-Q25 PAR_IN tRPHL RESET to PPO PPO QERR tRPLH RESET to QERR H, L, or X Figure 6. CY2SSTU32866 used as single device, C0=0, C1=0, RST# switchs from H to L Rev 1.0, November 25, 2006 IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII H or L IIIII IIIII IIIII Page 10 of 24 CY2SSTU32866 C0 = 0, C1 = 1 (RESET switches from L to H) RESET DCS CSR CLK CLK D1-D14 Q1-Q14 tsu PAR_IN th PPO QERR (not used) Figure 7. CY2SSTU32866 used as pair, C0=0, C1=1, RST# switches from L to H Rev 1.0, November 25, 2006 IIIII IIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII tact IIIIII IIIIII IIIIII IIII IIII IIII IIIII IIIII IIIII n n+1 n+2 n+3 n+4 tsu th tpdm, tpdmss CLK to Q tpd CLK to PPO tPHL CLK to QERR tPHL, tPLH CLK to QERR Data to QERR Latency H, L, or X H or L Page 11 of 24 CY2SSTU32866 RESET DCS CSR CLK CLK D1-D14 Q1-Q14 PAR_IN PPO QERR (not used) Unknown input event Rev 1.0, November 25, 2006 EEEEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEEEE EEEEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEEEE Figure 8. CY2SSTU32866 used as pair, C0=0, C1=1, RST# being held high EEEE EEEE CCCCCCCC CCCCCCCC EEEEEEEE EEEEEEEE CCCCC C CCC C CCCCC CCCC C CC C CCCC C CCCC CC C CCCC CC CCC C CCC CCC CCC tsu n n+1 n+2 n+3 n+4 th tpdm, tpdmss CLK to Q tsu th tpd CLK to PPO Data to PPO Latency tPHL or tPLH CLK to QERR Data to QERR Latency CCCC CCCC Output signal is dependent on the prior unknown input event H or L Page 12 of 24 CY2SSTU32866 RESET tinact DCS CSR CLK CLK D1-D14 tRPHL RESET to Q Q1-Q14 PAR_IN tRPHL RESET to PPO PPO QERR (not used) tRPLH RESET to QERR H, L, or X Figure 9. CY2SSTU32866 used as pair, C0=0, C1=1, RST# switches from H to L Rev 1.0, November 25, 2006 IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII H or L IIIII IIIII IIIII Page 13 of 24 CY2SSTU32866 RESET DCS CSR CLK CLK D1-D14 Q1-Q14 tsu th PAR_IN PPO (not used) QERR Data to QERR Latency Figure 10. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from L to H Rev 1.0, November 25, 2006 IIIII IIIII IIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIII IIIII IIIII IIIII IIIII tact n n+1 n+2 n+3 n+4 tsu th tpdm, tpdmss CLK to Q IIIIII IIIIII IIIIII tPHL CLK to QERR H, L, or X tpd CLK to PPO tPHL, tPLH CLK to QERR H or L Page 14 of 24 CY2SSTU32866 RESET DCS CSR CLK CLK D1-D14 Q1-Q14 PAR_IN PPO QERR (not used) Unknown input event Rev 1.0, November 25, 2006 E EEEEEEEEEEEE EEEEEEEEEE E EEEEEEEEEEEE EEEEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEEEE Figure 11. CY2SSTU32866 used as pair, C0=1, C1=1, RST# being held high EEEE EEEE CCCCCCCC CCCCCCCC EEEEEEEE EEEEEEEE C CCCCC CCC C CCCCC CCCC C CC C CCCC C CC CCCC C CCCC CCC CCC CCC CCC CCC tsu n n+1 n+2 n+3 n+4 th tpdm, tpdmss CLK to Q tsu th tpd CLK to PPO Data to PPO Latency tPHL or tPLH CLK to QERR Data to QERR Latency CCCC CCCC Output signal is dependent on the prior unknown input event H or L Page 15 of 24 CY2SSTU32866 C0 = 1, C1 = 1 (RESET switches from H to L) RESET tinact DCS CSR CLK CLK D1-D14 tRPHL RESET to Q Q1-Q14 PAR_IN tRPHL RESET to PPO PPO (not used) QERR tRPLH RESET to QERR H, L, or X Figure 12. CY2SSTU32866 used as pair, C0=1, C1=1, RST# switches from H to L Rev 1.0, November 25, 2006 IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII H or L IIIII IIIII IIIII Page 16 of 24 CY2SSTU32866 Absolute Maximum Conditions [1] Parameter TS VCC VIN VOUT IIK IOK IO ICCC Description Storage Temperature Supply Voltage Range Input Voltage Range[2, 3] Output Voltage Range[2, 3] VO < 0 or VO > VDD VO < 0 or VO > VDD VO = 0 to VDD Input Clamp Current Output Clamp Current Continuous Output Current Continuous Current through VDD/GND Condition Min. -65 -0.5 -0.5 -0.5 -50 -50 -50 -100 Max. 150 2.5 VDD + 0.5 VDD + 0.5 50 50 50 100 Unit C V V V mA mA mA mA DC Electrical Specifications Parameter TA (Com.) VDD VREF VTT VI II VIL VIH VIL VIH VICR VID VOL VOH IOH IOL IDD Description Ambient Operating Temp Operating Voltage Voltage Reference Terminating Voltage Input Voltage Input Current AC Input Low Voltage DC Input Low Voltage AC Input High Voltage DC Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input Differential Voltage Output Low Voltage Output High Voltage Output High Current Output Low Current Static Standby Power Supply Current Static Operating Power Supply Current RESET# = GND, IO = 0, VDD = 1.9V RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0, VDD = 1.9V IOL = 100 A, VCC = 1.7V to 1.9V IOL = 6 mA, VCC = 1.7V IOH = -100 A, VCC = 1.7V to 1.9V IOH = -6 mA, VCC = 1.7V CK, CK# RESET#, Cn 0.65 X VDD 0.675 600 - - VDD - 0.2 1.2 - - 1.125 - 0.2 0.5 - - -8 8 100 40 VI = VDD or GND Data, CSR#, and PAR_IN inputs Conditions Min. 0 1.7 0.49*VDD VREF-40mV 0 -5 - - VREF + 250mV VREF + 125mV Max. 70 1.9 0.51*VDD VREF+40mV VDD 5 VREF - 250mV VREF - 125mV - - 0.35 X VDD Unit C V V V V A V V V V V V V mV V V V V mA mA A mA Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5V (max.) Rev 1.0, November 25, 2006 Page 17 of 24 CY2SSTU32866 DC Electrical Specifications (continued) Parameter IDDD Description Conditions Min. Max. 28 (typical) Unit A/MHz RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, Power Supply Current Dynamic Operating Clock CK# switching 50% duty cycle, Only VDD = 1.8V Dynamic Operating per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration Low Power Active Mode, CLK only Low Power Active Mode per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, CS Enabled RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration, CS Enabled RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration; CS Enabled CIN Ci (Data and CSR#) Ci (CK and CK#) Ci (RESET#) VI = VREF 250mV VIX = 0.9V, VID = 600 mV VI = VDD or GND 2.5 2 2.5 18 (typical) A/MHz 36 (typical) A/MHz 27 (typical) A/MHz 2 (typical) A/MHz 2 (typical) A/MHz 3.5 3 pF pF pF AC Timing Specifications Parameter FCLK TW TACT[4] TINACT[5] TSU Description Clock Frequency Pulse Duration Differential Input Active time Differential Input Inactive time Set-up Time DSR# before crossing CK,CK#, CSR = H CSR# before crossing CK,CK#, DCS = H DCS# before crossing CK,CK#, CSR = L DODT, DCKE and data before crossing CK,CK#, CK going HIGH PAR_IN after crossing CK,CK# TH Hold Time DCS#, DODT, DCKE and data after crossing CK, CK# PAR_IN after crossing CK, CK# TPDM TPDMSS Propagation Delay single bit switching Propagation Delay simultaneous switching From CK, CK# crossing to Q From CK, CK# to Q simultaneous switching CK, CK# H or L Conditions Min. - 1 - - 0.7 0.7 0.5 0.5 Max. 500 - 10 15 - - - - Unit MHz ns ns ns ns ns ns ns 0.5 0.5 0.5 - - 1.86 1.87 ns ns ns ns ns ns Propagation Delay from Low to High From CK, CK# crossing to PPO 2.15 (typical) TPD Notes: 4. Data and VREF inputs must be low a minimum time of TACT max, after RESET# is taken HIGH. 5. Data, VREF and clock inputs must be held at valid levels (not floating) a minimum time of TINACT max after RESET# is taken LOW. Rev 1.0, November 25, 2006 Page 18 of 24 CY2SSTU32866 AC Timing Specifications (continued) Parameter TPLH TPHL TrPLH TrPHL SLR dv/dt Description Propagation Delay from Low to High Propagation Delay from Low to High Propagation Delay from Low to High Propagation Delay from High to Low Slew Rate Rising Slew Rate Falling Delta between Rising/Falling Rates Conditions From CK, CK# crossing to QERR# RESET# LOW to QERR# HIGH RESET# LOW to Q, PPO LOW dv/dt_r (20 to 80%) dv/dt_f (20 to 80%) 1 1 - Min. 1.2 1 3 (typical) 3 4 4 1 Max. 3 2.4 Unit ns ns ns ns V/ns V/ns V/ns DUT TL = 350ps, 50 CL = 30pF VDD RL = 1000 CK Inputs Test Point RL = 100 Test Point CK CK OUT Test Point RL = 1000 CL includes probe and jig capacitance Figure 13. Test Load for Timing Measurements #1 LVCMOS VDD RESET VDD/2 tinact IDD 10% IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA VDD/2 tact 90% 0V Figure 14. Active and Inactive Times tw VIH Input VICR VICR VID VIL VID = 600mV VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 15. Pulse Duration Rev 1.0, November 25, 2006 Page 19 of 24 CY2SSTU32866 CK VICR CK tsu Input VREF th VIH VREF VIL VID = 600mV VREF = VDD/2 VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs VID Figure 16. Set-up and Hold Times CK VICR CK tPLH Output VTT tPLH and tPHL are the same as tPD VICR tPHL VTT VI(P-P) VOH VOL Figure 17. Propagation Delay LVCMOS RESET Input VDD/2 tRPHL Output VTT VIH VIL VOH VOL tPLH and tPHL are the same as tPD VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 18. Propagation Delay after RESET# VDD DUT O UT R L = 50 Test Point C L = 10pF CL includes probe and jig capacitance Figure 19. Load Circuit - High to Low Slew Measurement Rev 1.0, November 25, 2006 Page 20 of 24 CY2SSTU32866 OUTPUT 80% dv_f 20% VOH VOL dt_f Figure 20. High to Low Slew Rate Measurement DUT OUT C L = 10pF Test Point R L = 50 CL includes probe and jig capacitance Figure 21. Load Circuit, Low to High slew measurement dt_r VOH 80% dv_r 20% OUTPUT VOL Figure 22. Low to High Slew Rate Measurement VDD DUT OUT RL = 1k T e s t P o in t CL = 10pF CL includes probe and jig capacitance Figure 23. Load Circuit - High to Low Slew Rate Measurement Rev 1.0, November 25, 2006 Page 21 of 24 CY2SSTU32866 Figure 24. Open drain output - Low to High transition with respect to reset inputs Timing Inputs VICR tPLH VICR VI(P-P) Output VCC/2 VCC VOL Figure 25. Open drain output - High to Low transition with respect to clock inputs Timing Inputs VICR tPLH VICR VI(P-P) VOH Output 0.15V 0V Figure 26. Open drain output - High to Low transition with respect to clock inputs DUT OUT CL = 5pF Test Point RL = 1K CL includes probe and jig capacitance Figure 27. Partial-parity-out Load Circuit Rev 1.0, November 25, 2006 Page 22 of 24 CY2SSTU32866 CK VICR CK tPLH Output VTT = VDD/2 tPLH and tPHL are the same as tPD VI(P-P) = 600mV VICR tPHL VTT VTT VI(P-P) VOH VOL Figure 28. Partial-parity-out ; propagation delay times with respect to clock inputs LVCMOS RESET INPUT VDD/2 tPHL VIH VIL VOH VOL Output VTT VTT = VDD/2 tPLH and tPHL are the same as tPD VIH = VREF + 250mV (AC Voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250mV ( AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs Figure 29. Partial-parity-out ; propagation delay times with respect to clock inputs Rev 1.0, November 25, 2006 Page 23 of 24 CY2SSTU32866 Ordering Information Part Number Lead Free CY2SSTU32866BFXC CY2SSTU32866BFXCT 96-pin FBGA 96-pin FBGA - Tape and Reel Commercial, 0 to 70 C Commercial, 0 to 70 C Package Type Product Flow Package Drawing and Dimensions 96-Ball FBGA (5.5 x 13.5 x 1.2 MM) BF96A O0.05 M C O0.25 M C A B O0.500.05(96X) TOP VIEW A1 CORNER BOTTOM VIEW A1 CORNER 1 A B C D 6.00 E F G 13.500.10 H J K L M 0.80 N P R T 13.500.10 12.00 2 3 4 5 6 6 5 4 3 2 1 A B C D E F G H J K L M N P R T DIMENSIONS IN MILLIMETERS REFERENCE JEDEC MO-205 PKG. WEIGHT: 0.23 gms PART # BF96A STANDARD PKG. BP96A LEAD FREE PKG. A B 5.500.10 A 2.00 0.80 4.00 0.530.05 0.400.05 0.25 C 0.15 C B 0.15(4X) 5.500.10 SEATING PLANE 0.26 C 1.20 MAX While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 25, 2006 Page 24 of 24 |
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